
China engineered a densely-packed chip without the one lithography machine sanctions block, but density on paper is not the same as speed in your hand, and the gap is still large.
What SemiAnalysis actually measured
SemiAnalysis (a chip-industry research firm) just published the first teardown from STEEL, its new in-house reverse-engineering lab, where analysts physically slice a chip apart and measure it under a microscope instead of trusting the maker's marketing.
The subject was SMIC N+3, the newest process from SMIC (Semiconductor Manufacturing International Corporation, China's largest chipmaker). A process, or 'node', is just a named recipe for building a chip generation. Two numbers stood out. The first is metal pitch, the spacing between the tiny metal wires layered onto a chip, where smaller means denser. SMIC N+3 hit a 32.5 nanometer minimum metal pitch, actually narrower than the 36 nanometer pitch in the 18A chips Intel is shipping right now. The second is transistor density: about 113.4 million transistors per square millimeter, just ahead of TSMC's mature N6 node (TSMC is the Taiwan Semiconductor Manufacturing Company, the world's leading contract chipmaker).
For a country locked out of the best chipmaking tools, matching Intel on one measurement and edging past a TSMC node on another is a real result, not a press release.
The simple version
The tool China cannot buy is an EUV machine (extreme ultraviolet lithography, which prints the finest chip patterns using very short-wavelength light). Only one company on earth, ASML in the Netherlands, makes them, each costs around 200 million dollars, and export rules keep them out of China.
So SMIC used the machine it can still buy: DUV (deep ultraviolet, an older tool with longer-wavelength light). One DUV pass draws lines too thick for a modern chip, so engineers run the same pattern through several carefully aligned passes, a technique called multi-patterning, to fake the fine detail EUV would print in one shot. It works. It is also slower, costlier, and more error-prone with every extra pass.
Here is the catch the density number hides. Packing transistors tightly is like cramming more books onto a shelf: impressive to look at, but it tells you nothing about how fast you can actually read them. Density is a photo of the layout. Performance is what the chip feels like when you use it, and those are two different things.
Density is a photo of the layout. Performance is what the chip feels like when you use it.
Is this new?
Not entirely, and that context matters. China surprised analysts once before, in 2023, when Huawei's Kirin 9000S shipped a 7-nanometer-class chip made on DUV, proving multi-patterning could clear a bar many assumed needed EUV. SMIC N+3 is the next rung on that same ladder, not a sudden leap.
What is new is the measurement. Instead of arguing over spec sheets and photos, SemiAnalysis physically took the silicon apart and counted. That is why the density figures land as credible, and also why the performance gap is hard to wave away.
The gap the headline number hides
Put the chip in a phone and the story changes. The Kirin 9030 Pro, built on SMIC N+3, powers Huawei's latest flagship. Against it, Qualcomm's Snapdragon 8 Elite Gen 5 (a current flagship chip) scores roughly 320 percent higher on single-core performance, the test of how fast one processor core runs. That is more than four times the speed on that measure. By SemiAnalysis's read, the Kirin's processor cores sit closer to flagship phones from around 2021.
So both things are true at once. On the workbench, SMIC N+3 looks dense and modern. In your hand, it runs like a phone from four years ago. A tight layout does not fix slower transistors, lower yields, or a costlier manufacturing path, and multi-patterning quietly adds all three.
On the workbench it looks modern. In your hand it runs like a phone from four years ago.
What it means
The honest reading is neither triumph nor dismissal. Sanctions did not stop China from building a dense chip, which is a meaningful engineering answer to a hard constraint. But they clearly did keep China a few years behind on the thing users actually feel, which is speed, cost, and efficiency at scale.
For anyone building with technology rather than trading the stocks, the useful lesson is smaller and more durable: a spec that looks cutting-edge on paper can still deliver a years-old experience. Whether it is a chip, a benchmark, or an AI model's headline number, measure the thing you care about, not the number that markets well.
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